Chia-Kai Yeh

Chai-Kai Yeh

Engineer

Paul Scherrer Institute
Forschungsstrasse 111
5232 Villigen PSI
Switzerland

CV

April 2019 – now: Engineer in Paul Scherrer Institut (PSI), Swizterland

  • SiC project: Optimize process & develop new process of SiC detectors.
  • ASML project: Process SEM inspection & EUV interference lithography.

May 2016 – Nov 2018:  Principal Product Engineer in Vanguard International Semiconductor Corporation (VIS), Taiwan.

  • Yield improvement: Drive yield from 83% to 96.6% at 0.15um high voltage products (TV source drivers).
  • Failure analysis: Investigate root cause of product low yield issues, such as design, device, and process issues.
  • Cross-departments cooperation: Work with external test and assembly sites to maximize electrical feedback to the factory. Integrate physical and electrical data to establish yield/ defect Pareto analysis and road-maps. Work closely with integration and process modules to improve yield.

May 2015 – May 2016: Senior Customer quality assurance engineer in Winbond Electronics Corporation (Winbond), Taiwan.

  • Return merchandise authorization (RMA) handling: a) 27 field return / line fall out issues (DRAM/Nor-flash) issues were solved. b) Failure analysis cycle time has been controlled well (Average: 6.81 working days; Target: 8 working days).

May 2007 – May 2014: Principal Product Engineer in Vanguard International Semiconductor Corporation (VIS), Taiwan.

  • Yield improvement: Drive yield from 90% to 97% at 0.16um high voltage products (mobile single chip driver IC) with embedded SRAM.
  • Transferring products into mass production: Successful improving yield of two phase-in (from NXP and Sharp) products and one transfer product (from tsmc) then kick them into mass production.
  • Failure analysis: Investigate root cause of product low yield issues, such as design, device, and process issues. Use data and electrical analysis, failure isolation, product and design information, device knowledge, and technology understanding to identify solutions. Include learning from test chips and test structures for yield limiter determination and improvement.
  • Cross-departments cooperation: Work with external test and assembly sites to maximize electrical feedback to the factory. Integrate physical and electrical data to establish yield/ defect Pareto analysis and road-maps. Work closely with integration and process modules to improve yield.

July 2006 – May 2007:  Research assistant in National Changhua University of Education (NCUE), Taiwan.

  • Ministry of Economic Affairs MRAM project assistant: a) Prepare TEM samples manually. b) Process magnetic tunnel junctions (MTJs) devices. c) Take care of utility of a laboratory (including a small clean-room).

Languages: Chinese/Taiwanese (Native speaker), English (B2), German (A1).

Failure Analysis Skills to solve products’ low yield issues or improve products’ yield:

  • Be familiar with Six Sigma DMAIC and 8D skills.
  • Data failure analysis: define failure modes and find suspected root causes by using Vanguard exploratory data analysis, Minitab and Microsoft Excel Macro…etc..
  • Electrical failure analysis: define failure location by using Parameter Analyzer / EMMI / InGaAs and layout tracing tool (Thunder: CAD tool).
  • Physical failure analysis: define failure layers by delayer skill with OM/SEM check. Package solder removed / re-ball / fix pins.
  • Analyze electrical parameters of individual devices in chips by using nano-probe.

Failure Analysis Tool Qualification:

  • Parameter Analyzer (HP4156), SEM (Hitach 4700/82xx), EMMI / OBIRCH / InGaAs (Hamamatsu Phemos-1000), Nano-probe.

Quality Certificates:

  • Six Sigma Green Belt Program Certificate, VIS, Taiwan.
  • IAFT16949 Automotive Quality Management System Standard, QDS, Taiwan.

Computer Certificate:

  • Level B technician for computer software application, Taiwan.

Interpersonal Course:

  • Dale Carnegie Training, Taiwan.

Teacher License:

  • High School Science, Taiwan.