It has been shown that timing measurements with an accuracy of less than four picoseconds are possible with the DRS4 chip.
In 2012, the design of the next generation chip has been started. The design goals are
- Increased analog bandwidth > 3 GHz
- Sampling speed 10 GSPS
- Dead-time less readout mode
- Analog FIFO mode for segment storage
- Internal triggering
- Deeper sampling depth, more channels
A first prototype of the inverter chain in the new 110 nm UMC technology has been designed and successfully tested in January 2013. A sampling speed of 10.6 GSPS has been achieved. First prototypes of this chips are however not expected before 2023.